Electronic Systems and Computer Systems (SESI)

The objective of this first year is to provide all the necessary bases for the hardware and software design of an embedded system.

Organization

The M1 year is divided into two semesters of 11 weeks each: the first semester starts at the beginning of September and the second at the beginning of February. Each semester, students take 5 UE of 6 credits (ECTS), for a total of 30 ECTS per semester. Students may be authorized to take a 6th UE, subject to the approval of the program responsible and a review of the previous results.

First semester (Master - S1)

The table below lists the UEs offered and the associated skill profiles. The ARCHI and VLSI courses are required for all profiles and are therefore mandatory. A number of courses are shared with the Communicating Systems stream of the Engineering Sciences Master's program (SPI), allowing students in the SESI stream to take some of the courses in this Master's programmes. It is also possible to choose UE from other Master programs in Computer Science (indicated by the lighter lines in the table).

Second semester (Master - S2)

The table below lists the courses offered in the second semester and the associated skills profile. The PPSE and ANG courses are mandatory and consist of 30 hours each, for a total of 6 ECTS. This offer can be supplemented with courses from other Master's program in Computer Science (indicated by the lighter lines in the table).

A student may, after consultation with the programm director and the course's responsible concerned, add units offered by other courses to their teaching contract, but in this case timetable compatibility cannot be guaranteed.

The aim of the second year of the SESI programme is to deepen the knowledge acquired in the first year and to enable students to acquire more specialised skills.

Organization

The first semester of M2 is dedicated to academic courses. Students have to choose 5 UE of 6 ECTS each. The second semester is dedicated to the final internship. This internship is worth 27 ECTS and the semester is completed by a professional integration course (OIP 3 ECTS), which is taken during the first semester of M2 (Master - S3).

Each UE in the first semester lasts approximately 60 hours. With the exception of one compulsory course, students are free to choose their specialisation, provided that they meet the requirements. Due to the specialisation of M2, the possibility of choosing UE from other programmes is extremely limited.

For the internship, students have to decide during the first semester whether they want to go into industry after the Master's degree or whether they want to do a PhD. In the former case, the final internship will be geared towards work experience in a company. In both cases, the subject must be approved by the programme director.

Third semester (Master - S3)

The table below lists the courses offered to students. The table also indicates the skills profile associated with each UE. 

The descriptions are provided for information only, as the content of the courses may change according to pedagogical constraints or developments in the fields concerned.

S1 - SESI - ARCHI : Architecture and design of RISC processors (6 ECTS)

• Presential, 20h CM + 40h TD
• UE taught in English and French.
• In this UE, we begin by presenting the architecture of the Mips-32 processor, then introduce the notion of pipeline execution. We detail the realization of the Mips-32 processor in a 5-stage pipeline and the consequences of this realization: the delayed effect of branching and the problem of data dependencies. We then present a superscalar 2-pipeline version of this architecture. We discuss code optimization techniques that attempt to make the most of these realizations: instruction reordering, loop unwinding and software pipelining. Finally, we turn our attention to the realization of the memory system. We introduce the notion of a memory hierarchy and the operating principles of this hierarchy: spatial and temporal locality. We detail the different types of caches. We then present the notion of virtual memory and the problem of translating virtual addresses into physical addresses.

S1 - SESI - VLSI : Design of digital integrated circuits (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• Starting from a paper specification, this course aims to present all the stages involved in designing a digital integrated circuit. Topics covered include Behavioral description in VHDL, setting up a test set, structural breakdown, description in gates of the architecture's constituent blocks, circuit placement and routing, and finally validation of the masks obtained: functional verification, verification of design rules and temporal characterization of the circuit. As this is an introductory course, the emphasis is on the principles of VLSI design. By the end of this course, students should be familiar with design methods, the different views of a circuit and, above all, the possible strategies for validating these views.

S1 - SESI - ESA : Electronics of analog systems (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This course introduces the structure and characteristics of analog integrated circuits (architecture and analysis of functionalities) and the basic elements of analog circuits. Modeling and simulation of analog/mixed-signal circuits are also covered.

S1 - SESI - MOBJ : Object modeling for circuit design (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This course, offered in priority to students coming from an electronics bachelor's degree, aims to introduce students to object structuring (absent in an electronics bachelor's degree). The applications of this course are oriented towards the modeling and realization of integrated circuits. C++ is used as a support language. Students will progressively build the key elements of a netlist viewer for VLSI circuits. The course focuses in particular on the methodology for moving from the abstract concept of a hypergraph (the netlist) to its decomposition into objects, and then to its implementation in C++. We also introduce the basic techniques for building a graphical interface using Qt, as well as the various classic software development tools.

S1 - SESI - SIGNAL : Signal processing (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This course introduces students to the basics of signal processing (discrete/sampled signals), filtering (particularly digital) and signal modulation. The detailed content of this course has been defined in consultation with the SESI programme and RES programme teaching teams, with a view to adapting it to both courses.

S1 - SAR - ARES : Network architecture (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This course is taught in English and French.
• The ARES course focuses on TCP/IP network architecture, studying the application, transport and network layers in IPv4 and IPv6 environments. This course has a strong practical component, enabling students to directly apply the concepts covered by analyzing traffic on an experimental network. The UE uses a specific local network platform and accesses international measurement platforms (SLICES/EdgeNet).

S1 - SAR - Kernel : Advanced architecture of operating system kernels (6 ECTS)

• Presential, 20h CM + 40h TD
• This study of advanced operating system kernel concepts focuses on the implementation of internal strategies for managing processor access, implementing virtual memories, organizing disks and caches, and accessing files. We analyze and compare the techniques and algorithms of the main Unix systems (BSD, Linux...) and Windows.

S1 - SAR - PSCR: Concurrent and Distributed System Programming (6 ECTS)

• Presential, 20h CM + 40h TD
• The aim of this course is to introduce and use the calls and services offered by an operating system to develop concurrent and distributed applications. We show how to solve concurrency and communication problems using the system primitives available in the POSIX standard. Notions covered include processes and threads, sockets, IPC (signals, shared memory, semaphores) and real time.

S2 - SESI - PPSE: Parallel Programming for Embedded Systems (3 ECTS)

• Presential, 30h CM/TD/TME
• The aim of this course is to introduce the general high-performance embedded architectures found in embedded systems, namely SIMD multicore processors and GPUs. These architectures are first presented separately (characteristics, programming model, strengths, weaknesses), along with their preferred application domains. This is important for understanding the areas of efficiency of these architectures and making optimization choices. The main high-level optimization techniques (algorithmic engineering, memory layout transformation) and low-level optimization techniques (loop nest transformation) are presented and applied to examples representative of the main application domains of embedded systems (signal and image processing, computer vision). Finally, optimization and load balancing problems are presented and put into practice in order to derive maximum performance from a hybrid architecture. Problems of autonomy and energy consumption are also addressed.

S2 - SESI - MULTI : Architecture of multiprocessor systems (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• taught in English and French
• This course analyzes the difficulties of coherence between memory and caches in the case of shared data, the problems posed by shared peripherals, and the hardware mechanisms supporting communication and synchronization between concurrent tasks in parallel multitasking applications. It presents the different hardware mechanisms used by the operating system to provide software applications with the various services they require: virtualization of memory, peripherals or the machine as a whole.

S2 - SESI - FPGA: Programmable Systems (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This course covers the implementation of digital systems on reconfigurable FPGA platforms, with particular emphasis on joint hardware/software design on these platforms. Topics covered include VHDL behavioral modeling, hardware IP development, and SOPC (System on a Programmable Chip) design. These aspects are applied in a mini-project.

S2 - SESI - IOC : Interface for communicating objects (6 ECTS)

• Presential, 20h CM + 40h TD/TME
• This UE presents the problem of creating interfaces between communicating objects. It covers two aspects of peripheral management: Using and writing generic peripheral drivers for the Linux system (character and USB kernel modules). Hardware and software implementation of an embedded system interfacing with the Linux system. The applications covered do not require any prerequisites in electronics.

S2 - SESI - PSESI : SESI project (6 ECTS)

• Completion of a project, alone or as part of a team, on a subject proposed by the course or between courses. The project is followed by a presentation of the detailed specifications approximately one month after the start of the project, and a final defense and report.

S2 - SPI - ECFA : Circuit electronics and analog functions (6 ECTS)

• Classroom-based, 20h CM + 40h TD/TME
• This course covers PLLs, DC-DC power supplies, A/D conversion and provides an introduction to analog circuit design.

S2 - SAR - AR : Distributed Algorithms (6 ECTS)

• Presential, CM 20h + TD 40h_
• This module deals with the algorithmic problems that arise when an application is made up of processes running on remote sites, with message communication and without access to shared memory. Solutions to several classical problems are presented: construction of the causal relationship, information diffusion by waves, detection of termination, reconstruction of a global state, etc.

S2 - SAR - COMNUM: Digital communications (6 ECTS)

• Presential, 20H CM + 40H TD
• This course provides an introduction to digital communications. The aim is to acquire the essential theoretical foundations needed to understand the various transmission processes implemented at the physical layer of networks, and to assess their performance and limitations.

S2 - SAR - PNL: Programming at the heart of the LINU kernel (6 ECTS)

• Presential, CM 20h + TD 40h
• The aim of this course is to study the operation of the Linux kernel and introduce students to “kernel programming”. Building on the concepts introduced in the first semester, it studies the algorithms and mechanisms implemented in the latest kernel versions. It also presents the structure of the Linux kernel, its APIs and the methodology required to develop new functionalities. Finally, it focuses on security issues in the kernel.

S3 - SESI - MASSOC : Modeling, analysis and simulation of on-chip embedded systems (6 ECTS)

• Presential, 60H CM/TME
• This compulsory course covers the modeling, simulation and verification of electronic and computer systems at different levels of abstraction. The use of modeling languages is developed, as well as the calculation models associated with them. Students is made aware of the problem of functional validation of a complex system, and is given an introduction to formal techniques. One of the supporting languages is SystemC and its derivatives for multiphysics systems.

S3 - SESI - COCAA : Advanced analog circuit design (6 ECTS)

• Presential, 60H CM/TME
• The aim of this course is to provide a practical introduction to the design and production of a complex analog integrated circuit. Examples include RF transceivers and analog-to-digital converters. Particular attention will be paid to design and analysis methods for these objects. This course uses tools commonly used in industry (Cadence, Eldo).

S3 - SESI - DSP: Digital signal processing (6 ECTS)

• Presential, 60H CM/TME
• This UE is dedicated to the design of electronic systems for intelligent and secure wireless communications. The following aspects are covered: study and modeling of digital wireless communication systems; realization of a wireless communication system using an SDR (Software Defined Radio) card; study of MIMO (Multiple Input Multiple Output) systems and digital beamforming; study of the security of wireless communication systems; realization of attacks on wireless communications; case studies are : Covert Channel and Jamming; using artificial intelligence to analyze digital wireless communication signals; building a digital integrated circuit to classify digital wireless communication signals.

S3 - SESI - IMSE: Hardware interface for embedded systems (6 ECTS)

• Presential, 60H CM/TME
• This course introduces students to the issues of power consumption in embedded systems (estimation, management and optimization of power consumption), noise (origins of intrinsic noise, noise parameters, low-noise calculations and design techniques) and signal integrity (transmission lines, crosstalk, parasitic signals, EMC). This course also addresses the problem of MEMS sensor implementation and interfacing.

S3 - SESI - HOTOP: Hot topics (seminars on emerging topics) (6 ECTS)

• Presential, 60H CM/TME
• This course is organized as a series of seminars. Each year, the course leaders identify topics of particular interest to industry or researchers. These topics are presented to students in seminar form by specialists in the field. The themes are renewed annually.

S3 - SESI - PACC: Parallelism and Accelerators for Cluster Computing (6 ECTS)

• Presential, 60H CM/TME
• This course is taught in English.
• This course focuses on the implementation of HPC applications for targets ranging from server computers to supercomputers. The most common programming models used in high-performance computing are studied and put into practice. This includes multithreaded programming, multinode programming and programming of computational gas pedals (vector instruction set, discrete GPU, NPU, etc.). A second objective of the course is to measure the performance of computational codes, with particular emphasis on the notion of scaling and the analysis of peak performance that is actually achievable (e.g. Roofline model). In other words, we will learn how to extract key metrics from calculation codes to understand the limiting points (in terms of software implementation and hardware architecture) and then apply a prediction model.

S3 - SESI - MOCCA : Methods and tools for advanced digital circuit design (6 ECTS)

• Presential, 60H CM/TME
• The aim of this course is to provide a practical introduction to the design of a complex VLSI circuit. On the one hand, the design method for modern digital circuits is presented, along with the tools needed to design these circuits and verify their realization for recent manufacturing technologies. On the other hand, we detail the realization techniques that enable performance targets to be met. For this UE, we are basing ourselves on industrial tools dedicated to the design of digital circuits in order to prepare students for the environment they will encounter in their working lives. First, we present the design methodology for digital integrated circuits, the various design stages from functional verification of a VHDL description to obtaining design masks and verification of the final circuit. We then show the tools commonly used in the industry to implement these steps (Cadence).

S3 - SESI - PBD-HLS : Platform based design - High level synthesis (6 ECTS)

• Presential, 60H CM/TME
• This course trains students in the advanced design of programmable systems-on-chip (SOPC), notably through a joint HW/SW design project on an FPGA platform, and in high-level synthesis (HLS), with methods and tools for moving from a high-level description of an application to its hardware implementation. The main points covered are: SOPC reminders; HW/SW partitioning; taking non-functional constraints into account in the design of a Pareto Front SOPC; performance evaluation (area, frequency, power consumption); high-level synthesis: from C algorithm to hardware implementation; FPGA implementation project.

S3 -SESI - SMC : Manycore system (6 ECTS)

• Presential, 60H CM/TME
• This UE focuses on the hardware realization of manycore architectures and on the implementation of operating systems for this type of architecture. It presents the fundamental principles of manycore architectures (several thousand cores) built around a shared address space and physically distributed memory and computing resources. It analyzes problems related to communications (on-chip micro-networks), synchronization (atomic locks and accesses), hardware mechanisms to support virtual memory, and techniques to guarantee cache consistency. We also address the problem of efficient application deployment on these architectures. We use the TSAR architecture as a hardware platform to illustrate the problems that can be encountered in manycore systems on both the hardware and software sides.